1. Field of the Invention
The present invention relates to a semiconductor memory device capable of preventing a failure in memory cells, which is caused by the breaking of a column address selection signal line.
2. Description of the Related Art
A semiconductor memory device such as a Dynamic Random Access Memory (DRAM) has a memory cell array comprised of a plurality of sub arrays. Each of the sub arrays has a plurality of word lines, a plurality of bit line pairs disposed so as to intersect the corresponding word lines, and a plurality of column address selection signal lines (column lines) arranged in parallel to the bit line pairs respectively. Memory cells are respectively connected to points where the word lines intersect the bit line pairs, and arranged in matrix form. The memory cell array is electrically connected with a row address decoder array and a column address decoder array.
A DRAM, for example, is disclosed in the Japanese Laid-Open Patent Publication No. 60-136087, published on Jul. 19th, 1985.